1. Field of the Invention
The invention relates to the field of manufacture of microelectronics fabrications. More particularly, the invention relates to the field of dielectric layers employed as inter-level metal dielectric (IMD) layers within microelectronics fabrications.
2. Description of the Related Art
Microelectronics fabrications employ patterned conductor layers to interconnect the various components out of which the microelectronics fabrications are built. As the density of components has increased and the dimensions of the components and interconnections of microelectronics fabrications have decreased, it has become necessary to employ multiple levels of interconnections to accomplish the wiring of the circuits of the microelectronics fabrication.
The conductor layers employed for interconnection levels in microelectronics fabrications are insulated from each other by dielectric layers formed between, over and under the interconnection levels and components. It is often necessary to separate a lower interconnection level from an upper level with a dielectric layer which may be required to have a number of properties. For instance, it is important that the upper surface of the dielectric layer be planar for photolithographic fabrication of the upper level patterned conductor layer. It is also critical that the physical integrity of the dielectric layer be sufficiently high to meet the design requirements of the microelectronics fabrication. The particular value of the dielectric constant of the dielectric layer may also be an important consideration.
For these and other reasons, the dielectric layer of an inter-level metal dielectric (IMD) layer employed in a microelectronics fabrication may in fact consist of several sub-layers of similar or different dielectric materials combined to obtain the desired properties. Various combinations are known in the art of silicon containing dielectric materials formed by different methods employed in a particular IMD layer, or of low dielectric constant organic polymer dielectric material employed in combination with silicon containing dielectric materials to achieve a particular result.
It is necessary to take into account the difference in both intrinsic material properties as well as the different methods of forming dielectric layers in order to employ properly combinations of materials and/or formation processes. Although combination of materials and methods are generally satisfactorily employed in forming inter-level metal dielectric (IMD) layers, such combination dielectric layers are not without problems.
The formation of a dense void-free layer of dielectric material on a substrate is often complicated by the need to cover over a variable topography of the substrate. In particular, the filling in of narrow gaps between features on a substrate surface with a high quality dielectric material may require a method of deposition which is not compatible with obtaining a planar surface. On the other hand, methods of formation which are suitable for gap filling may produce layers of dielectric material with inferior physical or electrical properties.
It is therefore towards the goal of forming an inter-level metal dielectric (IMD) layer with acceptable physical and electrical properties upon a substrate employed within a microelectronics fabrication that the present invention is generally and specifically directed.
Various methods have been disclosed for forming dielectic layers and specifcally inter-level metal dielectric (IMD) layers upon substrates employed within microelectronics fabrications.
For example, Jain, in U.S. Pat. No. 5,494,854, discloses a method for forming a dielectric layer stack within a microelectronics fabrication with enhanced plananzation of the uppermost layer. The composite dielectric stack consists of a conformal seed dielectric layer formed over the substrate, followed by a silicon dioxide layer formed by HDP-CVD methods, and finally a polishable layer of silicon oxide formed by plasma enhanced CVD from TEOS and dopant gases.
Further, Ahlburn et al., in U.S. Pat. No. 5,607,773, disclose a method for forming a dielectric stack layer upon a microelectronics fabrication with a low dielectric constant. The method employs a first silicon oxide dielectric layer formed employing plasma enhanced CVD of TEOS, followed by a low dielectric constant dielectric layer formed employing hydrogen silsesquioxane spin-on-glass (SOG) dielectric material, and finally a silicon oxide dielectric layer formed employing plasma enhanced CVD of TEOS.
Further still, Wang et al., in U.S. Pat. No. 5,679,606, disclose a method for forming a dielectric stack layer over interconnection lines upon a substrate wherein the first layer does not etch the substrate. The first silicon oxide dielectric layer is formed employing electron cyclotron resonance (ECR) without argon, followed by a gap filling silicon oxide layer formed by ECR with argon and RF power, and repeating the two formation processes until the desired thickness is built up.
Yet further still, Jang et al., in U.S. Pat. No. 5,786,262, disclose a method for forming a gap filling silicon oxide layer for filling shallow isolation trenches. The method employs an ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) method with TEOS to form the gap filling silicon oxide layer.
Still further, Yao et al., in U.S. Pat. No. 5,814,564, disclose a method for planarizing a dielectric stack layer consisting of a low dielectric constant dielectric spin-on-glass (SOG) layer formed over a silicon oxide dielectric layer. The silicon oxide layer is formed employing a high density plasma chemical vapor deposition (HDP-CVD) method. The planarization is carried out by a succession of etch back processes involving plasmas.
Finally, Huff et al., in U.S. Pat. No. 5,872,064, disclose a method for forming a dielectric stack layer with few voids and with compressive internal stress. The method employs a first conformal silicon oxide dielectric seed layer formed employing PECVD from TEOS, followed by a gap filling silicon oxide dielectric layer formed employing SACVD. The resulting stack is then sputter etched in argon to redistribute the silicon oxide dielectric material whose tensile stress balances the compressive stress of the seed layer and produce the final resulting compressive stress within the stack.
Desirable in the art of microelectronics fabrication are additional methods for forming inter-level metal dieletric (IMD) layers within substrates employed within microelectronics fabrications.
It is towards this goal that the present invention is generally and more specifically directed.
It is a first object of the present invention to provide a method for forming a dielectric layer upon a substrate employed within a microelectronics fabrication with optimized physical and dielectric properties.
It is a second object of the present invention to provide a method in accord with the first object of the present invention, where there is formed a composite inter-level metal dielectric (IMD) layer upon a semiconductor substrate employed within an integrated circuit microelectronics fabrication.
It is a third object of the present invention to provide a method in accord with the first and/or the second object of the present invention, where the present invention is readily commercially implemented.
In accord with the objects of the present invention, there is provided a method for forming upon a substrate employed within a microelectronics fabrication a composite inter-level metal (IMD) dielectric layer with optimized physical properties. To practice the invention, there is provided a substrate employed within a microelectronics fabrication. There is formed upon the substrate a patterned microelectronics layer. There is then formed upon the substrate a silicon oxide dielectric layer employing plasma enhanced chemical vapor deposition (PECVD). There is then formed over the silicon oxide layer a second dielectric silicon oxide layer formed employing ozone assisted sub-atmospheric pressure thermal chemical vapor deposition (SACVD) from tetra-ethyl-ortho-silicate (TEOS). Finally, a silicon oxide dielectric layer is formed over the substrate employing a high density plasma chemical vapor deposition (HDP-CVD) method. An additional silicon oxide layer formed employing PECVD may be formed over the third layer of HDP-CVD silicon oxide if desired.
The present invention provides a method for forming over a substrate employed within a microelectronics fabrication a composite inter-level metal dielectric (IMD) layer with optimized physical properties. The present invention may be employed with beneficial effect within microelectronics fabrications including but not limited to integrated circuit microelectronics fabrications, charge coupled device microelectronics fabrications, solar cell microelectronics fabrications, ceramic substrate microelectronics fabrications and flat panel display microelectronics fabrications.
The present invention employs materials and methods as are known in the art of microelectronics fabrications, but in a novel and original arrangement and sequence. The present invention is therefore readily commercially implemented.